A Technical Road Map from System Verilog to UVM

Abstract

As the fabrication technology is advancing more logic is being placed on a silicon die which makes verification more challenging task than ever. More than 70% of the design cycle is used for verification. To improve the time to market we need a reusable verification environment that detects all functional errors and avoid re-spin. Universal verification methodology was introduced to fulfill these goals. UVM is well structured, reusable with little or no modifications, do not interfere with the device under test (DUT) and gives the speed of verification. UVM is supported by all major simulator vendors, which was not in earlier methodologies. This methodology provides a standard unified solution that compiles on all tools. This paper introduces the advantages of UVM over System Verilog, basic terminologies used in UVM and a simple functional verification environment construction using UVM
DOI: 10.17762/ijritcc2321-8169.150389