Comparative Study of Spurious Power Suppression Technique Based Carry Look Ahead Adder And Carry Select Adder

Abstract

In the current era, speed and power being the essential characteristics of any digital circuit, emphasis is on designing low power, high speed adders. The significance of adder, a digital sub-system is well known by designers and engineers. Research is still going on adders by the design engineers by including new novel design techniques to speed up the circuit along with power reduction. It's difficult to design a digital adder with sufficient power reduction with the reduced propagation delay. Most demanding adder is the carry select adder which is very useful in digital processing systems to achieve faster arithmetic results. There is a possibility of reducing the power consumption, area and propagation delay in the existing Carry select adders. In this paper, spurious power suppression technique (SPST) based carry select adder (CSLA) and carry look ahead adder (CLA) have been designed using Verilog and compared.